HMC704LP4E【PDF 13/44 页】IC FRACT-N PLL 16BIT 24QFN

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5 - 20

HMC704LP4E

v03.1211

8 GHz fractionaL-n PLL

For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

rf Path ’n’ Divider

The main RF path ’N’ divider is capable of divide ratios anywhere between 219-1 (524,287) and 16 . This divider for ex-

ample could divide a 4GHz input to a PD frequency anywhere between its maximum output limit of 115MHz to as low as

7.6kHz. The ’N’ divider output may be viewed in test mode on LD_sDO by setting “Reg 0Fh”[4:0] = 10d. When operating

in fractional mode the N divider can change by up to +/-4 from the average value. Hence the selected divide ratio in

fractional mode is restricted to values between 219-5 (524,283) and 20.

If the VCO input is above 4GHz then the 8GHz fixed RF divide-by-2 should be used, “Reg 08h”[19] = 1. In this case the

total division range is restricted to even numbers over the range 2*(219-5) (1,048,566) to 40.

charge Pump and Phase Detector

The Phase Detector or PD has two inputs, one from the reference path divider and one from the RF path divider. When

in lock these two inputs are at the same average frequency and are fixed at a constant average phase offset with re-

spect to each other. We refer to the frequency of operation of the PD as fpd. Most formula related to step size, delta-sig-

ma modulation, timers etc., are functions of the operating frequency of the PD, fpd is sometimes referred to as the com-

parison frequency of the PD.

The PD compares the phase of the RF path signal with that of the reference path signal and controls the charge pump

output current as a linear function of the phase difference between the two signals. The output current varies in a linear

fashion over nearly ±2π radians (±360) of input phase difference.

Phase Detector and charge Pump functions

Phase detector register “Reg 08h” allows manual access to control special phase detector features.

“Reg 0Bh”[2:0] allows fine tuning of the PD reset path delay. This adjustment can be used to improve performance at

very high PD rates. Most often this register is set to the recommended value only.

“Reg 06h”[5] and [6] enables the PD UP and DN outputs respectively. Disabling prevents the charge pump from pump-

ing up or down respectively and effectively tri-states the charge pump while leaving all other functions operating inter-

nally.

CP Force UP “Reg 08h”[9] and CP Force DN “Reg 00h”[10] allows the charge pump to be forced up or down respec-

tively. This will force the VCO to the ends of the tuning range which can be useful for testing of the VCO.

PD Force Mid “Reg 0Bh”[11] will disable the charge pump current sources and place a voltage source on the loop filter

at approximately VPPCP/2. If a passive filter is used this will set the VCO to the mid-voltage tuning point which can be

useful for testing of the VCO.

“Reg 0Bh”[21:7] control other aspects of the phase detector operation and should be set to recommended values.

PLL Jitter

The standard deviation of the arrival time of the VCO signal, or the jitter, may be estimated with a simple approximation

if we assume that the locked VCO has a constant phase noise,

( )

, at offsets less than the loop 3dB bandwidth and

a 20dB per decade roll off at greater offsets. The simple locked VCO phase noise approximation is shown on the left of

Figure 30.

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